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www.irf.com 02 - apr - 10 ? 2010 international rectifier 1 1 1 august 2011 au irs2 3 34s 3 phase gate driver hv i c features ? floating channel d esigned for bootstrap operation ? fully operational to 6 00 v ? tolerant to negative transient voltag e, dv/dt immune ? gate drive supply range from 10 v to 20 v ? integrated dead time protection ? shoot - through (cross - conduction) prevention logic ? under - v oltage lockout for both channels ? independent 3 half - bridge drivers ? 3.3 v input logic compatible ? advanced input filter ? matched propagation delay for both channels ? lowe r di/dt gate driver for better noise immunity ? outputs in phase with inputs ? rohs compliant , lead free ? automotive qualified typical applications ? motor control ? low power fans ? general purpose inverters ? micro /mini inverter d rive r s product summary topology 3 phase v offset 6 00 v v out 1 0 v C 20 v i o+ & i o - (typical) 2 0 0 ma & 35 0 ma t on & t off (typical) 5 30 ns package options 20 l ead s wide body soic typical connecti on diagram hin 1 , 2 , 3 lin 1 , 2 , 3 ho 1 , 2 , 3 lo 1 , 2 , 3 up to 6 00v vcc lin 1 , 2 , 3 hin 1 , 2 , 3 to load v b 1 , 2 , 3 v s 1 , 2 , 3 vcc gnd com irs2 3 34
au irs2 334s www.irf.com ? 2010 international rectifier 2 table of contents page description 3 simplified block diagram 3 typical applic ation diagram 4 qualification information 5 absolute maximum ratings 6 recommended operating condition s 6 static electrical characteristics 7 dynamic electrical characteristics 7 functional block d iagram 8 input/output pin equivalent circuit diagram 9 lead definitions 1 0 lead assignments 1 0 application information and additional details 1 1 - 2 2 parameter temperature trends 2 2 - 2 5 package details 2 6 tape and reel details 27 part marking information 28 ordering information 28
au irs2 334s www.irf.com ? 2010 international rectifier 3 description the au irs2334 s is a high voltage, high speed power mosfet and igbt d river with three independent high side and low side referenced output ch annels for 3 - phase applications . proprietary hvic and latch immune cmos technology enables rug gedized monolithic construction . logic inputs are compatible with cmos o r lsttl outputs, d own to 3.3 v. the output drivers feature a high pulse current buffer stage designed for minimum driver cross - conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive n - channel powe r mosfets or igbts in the high side configuration up to 6 00 v. simplified block diagram h i g h s i d e i n p u t t o h i g h s i d e p o w e r s w i t c h e s ( x 3 ) c o m h v l e v e l s h i f t e r s d e l a y h v f l o a t i n g w e l l l o w s i d e i n p u t l o w s i d e o u t p u t t o l o w s i d e p o w e r s w i t c h e s ( x 3 ) h i g h s i d e o u t p u t v b h i g h s i d e p o w e r s u p p l y v s h i g h s i d e s u p p l y r e t u r n b o o t s t r a p d i o d e g n d s c h m i t t t r i g g e r , m i n i m u m d e a d t i m e a n d s h o o t - t h r o u g h p r o t e c t i o n v c c
au irs2 334s www.irf.com ? 2010 international rectifier 4 typical application diagram auirs2334 t o l o a d i r s 2 3 3 4 c o n t r o l i n p u t s v c c i n p u t v o l t a g e r a i l v o l t a g e
au irs2 334s www.irf.com ? 2010 international rectifier 5 qualification information ? qualification level automotive (per ae c - q100 ?? ) comments: this family of ics has passed an automotive qualification. ,5?v ,qgxvwuldo dqg &rqvxphu txdolilfdwlrq ohyho is granted by extension of the higher automotive level. moisture sensitivity level soic 20w msl3 ??? 260c (per ipc/jedec j - st d - 020) esd machine model class m2 (+/ - 150 v) (per aec - q100 - 003) human body model class h1b (+/ - 750 v) (per aec - q100 - 002) charged device model class c4 (+/ - 100 0 v) (per aec - q100 - 011) ic latch - up test class ii , level a (per aec - q100 - 004) rohs compliant y es ? 4xdolilfdwlrqvwdqgdugvfdqehirxqgdw,qwhuqdwlrqdo5hfwlilhu?vzhevlwh http://www.irf.com/ ?? exceptions (if any) to aec - q10 0 requirements are noted in the qualification report. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales representative for further information.
au irs2 334s www.irf.com ? 2010 international rectifier 6 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the d evice may occur. a ll voltage parameters are absolute voltages referenced to com unless otherwise specified . the thermal resistance and power dissipation ratings are measured under board mo unted and still air conditions . symbol definition min. max. units v b high side floating supply voltage - 0.3 6 2 5 v v s high side floating supply offset voltage v b1,2,3 - 2 5 ? v b 1,2,3 + 0.3 v ho 1,2,3 high side floating output voltage v s1,2,3 - 0.3 v b1,2,3 + 0.3 v cc low side and logic fixed supply voltage - 0.3 2 5 ? v lo 1, 2,3 low side output voltage - 0.3 v cc + 0.3 v in logic and analog i nput voltage s - 0.3 v cc + 0.3 pw hin high - side input pulse width 500 2 ns dv s /dt allowable offset supply voltage slew rate 2 50 v/ns p d package power dissipation @ ta
au irs2 334s www.irf.com ? 2010 international rectifier 7 static electrical characteristics u nless otherwise note d , these specifications apply for an operating junction temperature range of - 40 c ? tj ? 125 c with bias conditions of ( v cc - com ) = (v b 1,2,3 - v s 1,2,3 ) = 15 v . the v in and i in parameters are referenced to com . the v o and i o parameters are referenced to com and v s 1,2,3 and are applicable to the output leads l o 1,2,3 and h o 1,2,3 respective ly . the v cc uv and v bs uv parameters are referenced to com and v s respecti ve ly . symbol definition min. typ. max. units test conditions v ih /rjlf3lqsxwyrowdjh 2.5 2 2 v v il /rjlf3lqsxwyrowdjh 2 2 0.8 v in , th+ input positive going threshold 2 1.9 2 v in , th - input negative going threshold 2 1 2 v oh high level o utput voltage 2 0. 9 1.4 i o = 20 ma v ol low level output voltage 2 0.4 0.6 v ccuv+ v bsuv+ v cc and v bs supply under - voltage positive going threshold 10.4 11.1 11.6 v ccuv - v bsuv - v cc and v bs supply under - voltage negative going threshold 10.2 10.9 11.4 v ccuvh v bsuvh v cc and v bs supply under - voltage hysteresis 0. 0 5 0.2 2 i lk offset supply leakage current 2 1 50 a v b =v s = 6 00 v i qbs quiescent v bs supply current 2 4 0 120 v in = 0 v i qcc quiescent v cc supply current 2 3 00 700 a i in+ /rjlf3lq put bias current 2 150 25 0 a v in = 5 v i in - /rjlf3lqsxweldvfxuuhqw 2 1 v in = 0 v i o+ output high short circuit pulsed current 1 20 2 0 0 2 ma v o = 0 v or 15 v 3:??v i o - output low short circuit pulsed current 2 0 0 35 0 2 dynamic electrica l characteristics u nless otherwise note d , these specifications apply for an operating junction temperature range of - 40 c ? tj ? 125 c with bias conditions of v cc = v b 1,2,3 = 15 v, v s1,2,3 = com , and c l = 1000 pf unless otherwise specified. symbol definit ion min. typ. max. units test conditions t on turn - on propagation delay 400 530 750 ns v in = 0v and 5v t off turn - off propagation delay 400 530 750 t r turn - on rise time 2 125 190 t f turn - off fall time 2 50 75 t filin input filter time 200 35 0 51 0 dt dead time 1 8 0 290 420 v in = 0v & 5v external dead time 0s mdt dead time matching 2 2 7 0 mt t on , t off propagation delay matching time 2 2 60 pm p w p ulse width distortion ? 2 2 75 pw input =10s ? pm is defined as pw in - pw out .
au irs2 334s www.irf.com ? 2010 international rectifier 8 functio nal block diagram h i n 1 r e s e t s e t a u i r s 2 3 3 4 d e a d t i m e & s h o o t - t h r o u g h p r e v e n t i o n d e a d t i m e & s h o o t - t h r o u g h p r e v e n t i o n d e a d t i m e & s h o o t - t h r o u g h p r e v e n t i o n u v d e t e c t i n p u t n o i s e f i l t e r i n p u t n o i s e f i l t e r i n p u t n o i s e f i l t e r i n p u t n o i s e f i l t e r i n p u t n o i s e f i l t e r i n p u t n o i s e f i l t e r h i n 2 h i n 3 l i n 2 l i n 1 l i n 3 v b 1 v s 1 h o 2 v b 2 h o 1 v s 2 v b 3 h o 3 v s 3 v c c l o 1 l o 2 l o 3 c o m h v l e v e l s h i f t e r d e l a y d e l a y d e l a y l a t c h u v d e t e c t l a t c h u v d e t e c t l a t c h u v d e t e c t r e s e t s e t r e s e t s e t d r i v e r d r i v e r d r i v e r d r i v e r d r i v e r d r i v e r h v l e v e l s h i f t e r h v l e v e l s h i f t e r s d s d s d
au irs2 334s www.irf.com ? 2010 international rectifier 9 input/output pin equivalent circuit diagrams e s d d i o d e e s d d i o d e v c c l i n , h i n c o m r p u l l d o w n e s d d i o d e e s d d i o d e v b 1 , 2 , 3 h o 1 , 2 , 3 v s 1 , 2 , 3 e s d d i o d e e s d d i o d e l o 1 , 2 , 3 6 0 0 v 2 5 v c l a m p 2 5 v c l a m p v c c c o m
au irs2 334s www.irf.com ? 2010 international rectifier 10 lead definitions symbol description vcc low side and logic power supply vb1 high side floa ting power supply (phase 1) vb2 high side floating power supply (phase 2) vb3 high side floating power supply (phase 3) vs1 high side floating supply return (phase 1) vs2 high side floating supply return (phase 2) vs3 high side floating supply return (phase 3) hin1 logic input for high side gate driver output ho 1 , input is in - phase with output hin2 logic input for high side gate driver output ho 2 , input is in - phase with output hin3 logic input for high side gate driver output ho 3 , input is in - phase with output lin1 logic input for low side gate driver output l o 1 , input is in - phase with output lin2 logic input for low side gate driver output l o 2 , input is in - phase with output lin3 logic input for low side gate driver output l o 3 , input is in - phase w ith output ho1 high side gate driver output (phase 1) ho2 high side gate driver outp ut (phase 2) ho3 high side gate driver output (phase 3) lo1 low side gate driver output (phase 1) lo2 low side gate driver output (phase 2) lo3 low side gate driver o utput (phase 3) com low side supply return lead assignments 20 leads wide body soic 1 2 3 4 5 6 7 1 4 1 5 1 6 1 7 1 8 1 9 2 0 h i n 1 h i n 2 h i n 3 l i n 1 l i n 2 l i n 3 c o m v b 1 h o 1 v s 1 h o 2 v s 2 v b 3 8 9 1 0 1 1 1 2 1 3 l o 3 l o 2 l o 1 v s 3 v c c v b 2 h o 3
au irs2 334s www.irf.com ? 2010 international rectifier 11 application information and additional details x igbt/mosfet gate drive x switching and timing relationships x deadtime x matched propagation delays x input logic compatibility x shoot - through protection x under - v oltage lockout protection x trut h table: under - voltage lockout x advanced input filter x short - pulse and noise rejection x tolerant to negative v s transients x pcb layout tips x additional documentation igbt/ mosfet gate drive the au irs2334 hvic is designed to drive high side and low side mosfet or igbt power devices. figure s 1 and 2 show the definition of some of the relevant par ameters associated with the gate d rive r output functionality. the output current that drive s the gate of the external power switch es is defined as i o . the output voltage that drive s the gate of the external power switch es is defined as v ho for the high sid e and v lo for the low side; this parameter is sometimes generically called v out and in this case the high side and low side outp ut voltages are not differentiated. figure 1 : hvic sourcing curren t figure 2 : hvic sinking current v s ( or com ) h o ( or lo ) v b ( or v cc ) i o + v h o ( or v l o ) + - v s ( or com ) h o ( or lo ) v b ( or v cc ) i o -
au irs2 334s www.irf.com ? 2010 international rectifier 12 switching and tim ing relationships the relationship between the input and output signals of the au irs2334 hvic is shown in figure 3 . t he definitions of some of the relevant parameters associated with the gate d rive r in put to output transmission are given . figure 3 : switching time waveforms during interval a of figure 4 the hvic receives the c ommand to turn on both the high and low side s witches at the same time ; correspondingly, the s hoot - through protection prevents the high and low side signals ho and lo turn on by keeping them low . figure 4 : input/output timing diagram deadtime the au irs2334 hvic provides an integrate d deadtime protection circuitry . the deadtime interval for this hvic is fixed; while rwkhu,&vzlwklq,5?v+9, c portfolio feature programmable deadtime for greater design flexibility. the deadtime feature inserts a time interval in which both the gate drive r outputs lo and ho are held o ff; to ensure that the power switch being turned off has fully turned off before the se cond power switch is turned on. this minimum deadtime is automatically inserted whenever the external deadtime commanded by the host lin or hin 50 % 50 % pw in pw out 10 % 10 % 90 % 90 % t off t on t r t f lo or ho h o l o h i n l i n a
au irs2 334s www.irf.com ? 2010 international rectifier 13 mic rocontroller is shorter than dt, while external deadtimes larger than dt are not modified by the gate driver. figure 7 illustrates the deadtime interval definition and the relationship between the output gate signals. the deadtime interval introduced is matched with respect to the commut ation from hin turning off to lin turning on, and viceversa. figure 5 defines the two deadtime parameters dt1 and dt2 . the dea dtime matching parameter mdt is defined as the maximum difference between dt1 and dt2. figure 5 : de ad time definition matched propagation delays the au irs2334 hvic is designed for propag ation delay matching. with this feature, the input to output propagation delay s t on , t off are the same for the low side and the high side channels ; the maximum differ ence being specified b y the delay matching parameter mt as defined in figure 6 . figure 6 : delay matching waveform definition input logic compatibility the au irs2334 hvic is designed with inputs compatible with standard cmos and ttl outputs with 3.3 v and 5 v logic level signals . figure 7 shows how an input signal is logically interpreted . hin lin 50 % 50 % 50 % 50 % dt2 dt1 ho lo h i n l i n 5 0 % 5 0 % h o l o 1 0 % 9 0 % l o h o m t m t
au irs2 334s www.irf.com ? 2010 international rectifier 14 figure 7 : hin & lin input thresholds shoot - through protection the au irs2334 is equipped with a shoot - through protection circui try which prevents cross - conduction of the power switches. table 1 shows the input to output relationship in the form of a truth table. note that the hvic has non - inverting inputs (the output is in - phase with the respective input). hin lin ho lo 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 table 1: input/output truth table under - v oltage lockout protection the au irs2334 hvic provides under - voltage lockout protection on both the v cc l ow side and logic fixed power supply and the v bs high side floating power s upply. figure 8 illustrate s this concept by considering the v cc (or v bs ) plotted over time : as the waveform crosses the uvlo threshold , the under - voltage protection is entered or exited . upon power up, s hould the v cc voltage fail to reach the v ccuv + thres hold, the gate drive r outputs lo and ho will remain disabled . additionally, if the v cc voltage decreases below the v ccuv - threshold during normal operation, the under - voltage lockout circuitry will shutdown the gate drive r outputs lo and ho. upon power up , s hould the v bs voltage fail to reach the v bsuv threshold, the gate driver output ho will remain disabled . additionally, if the v bs voltage decreases below the v bsuv threshold during normal operation, the under - voltage lockout circuitry will shutdown the high side gate drive r output ho . the uvlo protection ensure s that the hv ic drives external power devices only with a gate supply voltage sufficient to fully enhance them. without this protection , the gates of the external power switch es could be driven i n p u t s i g n a l v i h v i l i n p u t l o g i c l e v e l h i g h l o w l o w
au irs2 334s www.irf.com ? 2010 international rectifier 15 wi th a low voltage, which would result in power switches conducting current while with a high channel impedance , which would produce very high conduction losses possibly lead ing to power device failure. figure 8 : uvlo protectio n truth table: under - v oltage lockout table 2 provide s the truth table for the au irs2334 hvic . the 1 st line shows that for v cc below the uvlo threshold both the gate drive r outputs lo and ho are disabled. a fter v cc returns above v ccuv , the gate drive r outputs return functional . the 2 nd line shows that for v bs below the uvlo threshold, the gate drive r output ho is disabled. after v bs returns above v bsuv , ho remains low until a new rising transition of hin is received. the last line shows the normal ope ration of the hvic . vcc vbs outputs lo ho uvlo v cc < v ccuv 0 0 uvlo v bs 15 v < v bsuv lin 0 normal operation 15 v 15 v lin hin table 2 : uv lo t ruth table advanced input filter the au irs2334 hvic provides an advanced input filter that improves the input/output pulse symmetry of the signals processed by the hvic. this input filter is inserted a t the hin and lin input pin s. the working principle of the filter is shown in figures 9 and 1 0 . figure 9 shows a typical input filter and the asymmetry it produces on its output signal . the upper waveforms of example 1 show an input signal with a pulse duration mush longer th a n the filtering time t filin ; the resulting output v ccu v - ( or v bsu v - ) uvlo protection ( gate driver outputs disabled ) norma l operation norma l operation v ccu v + ( or v bsu v + ) v cc ( or v b s ) time
au irs2 334s www.irf.com ? 2010 international rectifier 16 signal ha s a duration given approximately by the difference between the input signa l and t filin . the lower waveforms of example 2 show an input signal with a pulse duration slightly longer th a n the filtering time t filin ; the resulting output signal ha s a duration given approximately by the difference between the input signal and t filin, much shorter than it should be. figure 10 shows the advanced input filter and the symmetry it produces on its output signal . the upper waveforms of example 1 show an input signal with a pulse duration much longer th a n the filtering time t filin ; the result ing output signal ha s approximately the same duration as the input signal. the lower waveforms of example 2 show an input signal with a pulse duration slightly longer th a n the filtering time t filin ; the resulting output signal ha s approximately the same du ration as the input signal . figure 9 : typical input filter figure 1 0 : advanced input filter short - pulse and noise rejection the advanced input filter that improves the input/output pulse symmetry of the signals processed by the hvic also helps th e reject ion of noise spikes and of short pulses on the input signals . i nput signal s with a pulse duration less than the filtering time t filin will be filtered out. in figure 11 example 1 shows an input signal in the low state with superimposed po sitive no ise spikes of duration less than t filin ; the advanced input filter filters out the noise spikes and the output signal remains in the low state . example 2 shows an input signal in the high state with superimposed negative noise spikes of duration less than t filin ; the advanced input filter filters out the noise spikes and the output signal remains in the high state . figure 11 : noise rejection of the advanced input filter t f i l , i n i n o u t i n o u t e x a m p l e 1 e x a m p l e 2 t f i l , i n t f i l , i n t f i l , i n i n o u t i n o u t e x a m p l e 1 e x a m p l e 2 i n o u t e x a m p l e 1 e x a m p l e 2 i n o u t t f i l , i n t f i l , i n
au irs2 334s www.irf.com ? 2010 international rectifier 17 the measured characteristic of the advanced input filter is shown in figure 12. on the left side the characteristic for narrow on pulse s is shown (short positive pulse) while on the left side the characteristic for narrow off pulse s is shown (short negative pulse) . the x - axis represents the input pulse duration pw in , while the y - axis th e resulting output pulse duration pw out . f or pulses with input pulse duration pw in less than the filtering time t filin the resulting output pulse duration pw out is zero because the filter rejects the input signal . f or pulses with input pulse duration pw in greater than the filtering time t filin the resulting output pulse duration pw out tracks the input pulse durations well , the higher the duration the better the symmetry . figure 1 2 : measured advanced i nput filter characteristic the difference between the output pulse duration pw out and the input pulse duration pw in of both the narrow on and narrow off cases is shown in figure 13 . the x - axis represents the input pulse duration pw in , while the y - axis the resulting difference pw out pw in . figure 13 : difference between the input pulse duration and the output pulse duration tolerant to negative vs transients $ frpprq sureohp lq wrgd\?v kljk - power switching converters is the transient response of the vzlwfk qrgh?v voltage as the power devices switch on and off quickly while carrying a large current. a typical 3 - phase inverter circuit is shown in figure 14 ; w here we define the power switches and diodes of the inverter. i f the high - side switch (e.g., the igbt q1 in figures 1 5 and 1 6 ) switches off, whi le the u phase current is flowing to an inductive load, a current commutation occurs from high - side switch (q1) to the diode (d2) in parallel with the low - side s witch of the same inverter leg. at the same instance, the voltage node v s1 , swings from the pos itive dc bus voltage t o the negative dc bus voltage. n a r r o w p u l s e o n 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 t i m e ( n s ) t i m e ( n s ) p w o u t p w i n n a r r o w p u l s e o f f 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 t i m e ( n s ) t i m e ( n s ) p w o u t p w i n n a r r o w p u l s e o n 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 t i m e ( n s ) t i m e ( n s ) p w o u t - p w i n s h o r t p u l s e f i l t e r e d n a r r o w p u l s e o f f 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 t i m e ( n s ) t i m e ( n s ) p w o u t - p w i n s h o r t p u l s e f i l t e r e d
au irs2 334s www.irf.com ? 2010 international rectifier 18 figure 14 : three phase inverter figure 1 5 : q1 conducting figure 1 6 : d2 conducting also when the v phase current flows from the inductive load back to the inverter (see figures 1 7 and 1 8 ), an d q4 igbt switches on, the current commutation occurs from d3 to q4. at the same instance, the voltage node, v s2 , swings from the positive dc bus voltage to the negative dc bus voltage. figure 1 7 : d3 conducting figure 1 8 : q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the negative dc bus, rather it vzlqjvehorzwkhohyhoriwkhqhjdwlyh'&exv7klvxqghuvkrrwyrowdjhlvfdoohg3qhjdwlyh9 s wudqvlhqw i n p u t v o l t a g e d c + b u s t o l o a d q 1 q 2 q 3 q 4 q 5 q 6 d 1 d 2 d 3 d 4 d 5 d 6 u v w d c - b u s v s 1 v s 2 v s 3 q 1 o n d 2 v s 1 q 2 o f f i u d c + b u s d c - b u s d c + b u s q 1 o f f d 1 d 2 d c - b u s v s 1 q 2 o f f i u d c + b u s q 3 o f f d 3 d 4 d c - b u s v s 2 q 4 o f f i v d c + b u s q 3 o f f d 3 d c - b u s v s 2 q 4 o n i v
au irs2 334s www.irf.com ? 2010 international rectifier 19 the circuit shown in figure 1 9 depicts one leg of the three phase inverter; figures 20 and 21 show a simplified illustration of the commutation of the current between q1 and d2. the parasitic inductances in the power circuit from the die bonding to the pcb tracks are lumped together in l c and l e f or each igbt . when the high - side switch is on, v s1 is below the dc+ voltage by the voltage drops associated with the power switch and the par asitic elements of the circuit. when the high - side power switch turns off, the load current momentarily flows in th e low - side freewheeling diode due to the inductive load connected to v s1 (the load is not shown in these figures). this current flows from the dc - bus (which is connected to the com pin of the hvic) to the load and a negative voltage between v s1 and the dc - bus is induced (i.e., the com pin of the hvic is at a higher potential than the v s pin). figure 1 9 : parasitic elements figure 20 : v s positive figure 21 : v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 3 - 5 v/ns. the negative v s transient voltage can exceed this range during some events such as short circuit and over - current shutdown, when di/dt is greater than in normal operation. ,qwhuqdwlrqdo 5hfwlilhu?v +9,&v kdyh ehhq ghvljqhg iru wkh urexvwqhvv uhtxluhg lq pdq\ ri wrgd\?v ghpdqglqj applicatio ns. an indication of the au irs2334 ?vurexvwqhvvfdqehvhhqlq)ljxuh 22 , where there is represented the au irs2334 safe operating area at v bs =15v based on repetitive negative v s spikes. a negative v s transie nt voltage falling in the grey area (outside soa) may lead to ic permanent damage; vice versa unwanted functional anomalies or permanent damage to the ic do not appear if negative vs transients fall inside soa. at v bs =15v in case of - v s transients greater than - 16.5 v for a period of time greater than 50 ns; the hvic will hold by design the high - vlghrxwsxwvlqwkhriivwdwhiruv d c + b u s d 1 d 2 d c - b u s v s 1 q 1 q 2 l c 1 l e 1 l c 2 l e 2 d c + b u s d c - b u s q 1 o n d 2 q 2 o f f v s 1 v l c 1 + - v l e 1 + - i u d c + b u s q 1 o f f d 1 d c - b u s q 2 o f f v s 1 v l c 2 - + v l e 2 - + i u v d 2 - +
au irs2 334s www.irf.com ? 2010 international rectifier 20 figure 22 : negative v s transient soa @ vbs=15v even though the au irs2334 has been shown able to handle these large n egative v s transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layout and component use.
au irs2 334s www.irf.com ? 2010 international rectifier 21 pcb layout tips distance between high and low voltage components: it ?vvwurqjo\uhfrpphqghgwrsodfhwkhfrpsrqhqwvwlhgwr the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. please see the case outline information in this datasheet for the details. ground plane: i n order to min imize noise coupling, the ground plane should not be placed under or near the high volta ge floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise ( s ee figure 23 ). in order to reduce the em couplin g and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collector - to - gate parasitic capacitance . the parasitic auto - inductan ce of the gate loop contributes to developing a voltage across the gate - emitter, thus increasing the possib ility of a self turn - on effect. figure 23 : antenna loops supply capacitor: it is recommended to place a bypass capac itor between the vcc and com pins. this connection is shown in figure 24 . $ fhudplf ) fhudplf fdsdflwru lv suitable for most applications. this component should be placed as close as possible to the pins in order to reduce parasitic elements. figure 24 : supply c apacitor r g v ge gate drive loo p c gc i gc v b ( or v cc ) h o ( o r lo ) v s ( or com ) hin 1 , 2 , 3 lin 1 , 2 , 3 ho 1 , 2 , 3 lo 1 , 2 , 3 up to 6 00v vcc lin 1 , 2 , 3 hin 1 , 2 , 3 to load v b 1 , 2 , 3 v s 1 , 2 , 3 vcc gnd com
au irs2 334s www.irf.com ? 2010 international rectifier 22 routing and placement: power stage pcb parasitic elements can contribute to large negative voltage transients a t the switch node; it is recommended to limit the pha se voltage negative transients. in order to avoid such conditions, it is recommended to 1) minimize the high - side source to low - side collector distance, and 2) minimize the low - side emitter to nega tive bus rail stray inductance. however , where negative v s spikes remain excessive, further steps ma y be taken to reduce the spike. 7klvlqfoxghvsodflqjduhvlvwru ruohvvehwzhhqwkh9 s pin and the switch node (see figure 2 5 ), and in some cases using a clamping diode between com and v s (see figure 2 6 ). see dt04 - 4 at www.irf.com for more deta iled information. figure 2 5 : v s r esistor figure 2 6 : v s c lamping diode additional documentation several technical documents related to the use of hvics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these documents. dt97 - 3 : managing transients in control ic driven power stages an - 1123: bootstrap network analysis: foc using on the integrated bootstrap functionality dt04 - 4 : using monolithic high voltage gate drivers an - 978: hv floating mos - gate driver ics parameter temperature trends figures 2 7 - 44 provide information on the experimental performance of the au irs2334 hv ic. the line plotted in each figure is generated from actual experimental data. a small number of individual samples were tested at three temperatures ( - 40 oc, 25 oc, and 125 oc) in order to generate the experimental curve. the line labeled exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood temperature trend. the individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). to load v s ho v b l o co m r vs dc + bu s dc - bu s c bs t o load v s ho v b l o co m r vs d vs dc + bus dc - bus c bs
au irs2 334s www.irf.com ? 2010 international rectifier 23 fig. 2 7 . turn - on propagation delay vs. temperature fig. 2 8 . turn - off propagation delay vs. temperature fig. 2 9 . turn - on rise time vs. temperature fig. 30 . turn - off fall time vs. temperature fig. 31 . high level output voltage (i o = 2 0 m a) vs. temperature fig. 32 . low level output voltage (i o = 2 0 m a) vs. temperature 500 525 550 575 600 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on propagation delay (ns) typ. m ax. m in. 450 500 550 600 650 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off propagation delay (ns) typ. m ax. m in. 75 100 125 150 175 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on rise time (ns) typ. m ax. m in. 30 40 50 60 70 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off fall time (ns) - typ. m ax. m in. 500 700 900 1,100 1,300 -50 -25 0 25 50 75 100 125 temperature ( o c) high level output voltage (mv) . typ. m ax. m in. 150 200 250 300 350 400 -50 -25 0 25 50 75 100 125 temperature ( o c) low level output voltage (mv) typ. m ax m in.
au irs2 334s www.irf.com ? 2010 international rectifier 24 fig. 33 . offset supply leakage current vs. temperature fig. 34 . quiescent vcc supply current vs. temperature fig. 3 5 . input filter delay time vs. temperature fig. 3 6 . quiescent vbs supply current vs. temperature fig. 3 7 . vcc supply under - voltage positive going threshold vs. temperature fig. 3 8 . vcc supply under - voltage negative going threshold vs. t emperature 0 4 8 12 16 -50 -25 0 25 50 75 100 125 temperature ( o c) offset supply leakage current (ua). typ. m ax. m in. 0.00 0.25 0.50 0.75 1.00 -50 -25 0 25 50 75 100 125 temperature ( o c) quiescent v cc supply current (ma) typ. m ax. m in. 225 275 325 375 425 -50 -25 0 25 50 75 100 125 temperature ( o c) input filter time (ns) . typ. m ax. m in. 20 30 40 50 60 -50 -25 0 25 50 75 100 125 temperature ( o c) quiescent v bs supply current (ua) typ. m ax. m in. 10.50 10.75 11.00 11.25 11.50 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc supply uv+ going threshold (v) typ. m ax. m in. 10.30 10.55 10.80 11.05 11.30 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc supply uv- going threshold (v) typ. m ax . m in.
au irs2 334s www.irf.com ? 2010 international rectifier 25 fig. 3 9 . vbs supply under - voltage positive going threshold vs. temperature fig. 40 . vbs supply under - voltage negative going threshold vs. temperature fig. 41 . output low short circuit pulsed current vs. temperature fig. 42 . output high short circuit pulsed current vs. temperature 10.50 10.75 11.00 11.25 11.50 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs supply uv+ going threshold (v) typ. m ax. m in. 10.30 10.55 10.80 11.05 11.30 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs supply uv- going threshold (v) typ. m ax. m in. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) io- (ma) exp. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) io+ (ma) exp.
au irs2 334s www.irf.com ? 2010 international rectifier 2 6 package details
au irs2 334s www.irf.com ? 2010 international rectifier 27 tape and reel details carrier tape dimension for 20soicw cod e mi n ma x min ma x a 11.9 0 12.1 0 0.46 8 0.47 6 b 3.9 0 4.1 0 0.15 3 0.16 1 c 23.7 0 24.3 0 0.93 3 0.95 6 d 11.4 0 11.6 0 0.44 8 0.45 6 e 10.8 0 11.0 0 0.42 5 0.43 3 f 13.2 0 13.4 0 0.52 0 0.52 8 g 1.5 0 n/ a 0.05 9 n/ a h 1.5 0 1.6 0 0.05 9 0.06 2 reel dimensions for 20so icw cod e mi n ma x min ma x a 329.6 0 330.2 5 12.97 6 13.00 1 b 20.9 5 21.4 5 0.82 4 0.84 4 c 12.8 0 13.2 0 0.50 3 0.51 9 d 1.9 5 2.4 5 0.76 7 0.09 6 e 98.0 0 102.0 0 3.85 8 4.01 5 f n/ a 30.4 0 n/ a 1.19 6 g 26.5 0 29.1 0 1.0 4 1.14 5 h 24.4 0 26.4 0 0.9 6 1.03 9 metri c imperial metri c imperial e f a c d g a b h note : controlling dimension in mm loaded tape feed direction a h f e g d b c
au irs2 334s www.irf.com ? 2010 international rectifier 28 part marking information ordering inf ormation base part number package type standard pack complete part number form quantity au irs2334 soic 20w tube/bulk 36 au irs2334 s tape and reel 1000 au irs2334 str a u i r s 2 3 3 4 i r l o g o a y w w ? p a r t n u m b e r d a t e c o d e p i n 1 i d e n t i f i e r l o t c o d e ( p r o d m o d e 4 d i g i t s p n c o d e ) a s s e m b l y s i t e c o d e p e r s c o p 2 0 0 - 0 0 2 ? x x x x m a r k i n g c o d e l e a d f r e e r e l e a s e d n o n - l e a d f r e e r e l e a s e d ? p
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